1. Field of the Invention
The present invention relates to an epitaxial silicon wafer and a fabrication method thereof. More particularly, the present invention relates to a technique suitable for use in a silicon wafer having a plane inclined from a {110} plane as a main surface.
Priority is claimed on Japanese Patent Application No. 2006-240866, filed Sep. 5, 2006, and on Japanese Patent Application No. 2007-228717, filed Sep. 4, 2007, the content of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, the feasibility of semiconductor integrated circuit devices has been increased in which a so-called {110} silicon wafer, in which a main surface is a {110} plane of a silicon single crystal or a plane in the vicinity of the {100} plane, is used. Such a {110} silicon wafer has a high probability of increasing a carrier mobility in the MOSFET channel direction compared to that obtainable from the conventional {100} wafer, and thus application of the {110} silicon wafer to logic devices is expected.
[Patent Document 1] JP-A-2004-265918
The epitaxial wafers having an epitaxial layer grown on the {110} silicon wafer has a problem in that the surface roughness after the epitaxial growth may be degraded compared to the epitaxial wafers having an epitaxial layer grown on the {100} wafer.
Such degradation in the surface roughness may result in degradation in the haze level measured by a surface inspection tool and thus has a substantial influence on the measurement values since the degraded surface roughness is treated as noise when measuring micro-size LPDs (light point defects) on the surface as required by high-precision products.
In view of the effect of the surface roughness on the noise, at the present moment, it is difficult to measure LPDs of 100 nm or less on the surface of the {110} epitaxial wafer at the time of wafer surface inspection. Thus, it is difficult to determine the surface state of the wafer, making it impossible to perform a quality evaluation on the wafer.